1. Field of the Invention
The present invention relates to a solid stage image sensor of a charge-coupled device (CCD) type and its manufacturing method. More particularly, the present invention relates to a charge-coupled device and its manufacturing method in which device characteristics are improved so that excellent charge transfer efficiency can be maintained.
2. Description of the Related Art
As is well-known, a solidification of image sensors having a matrix type arrangement was first proposed in the early 1960's. However, solidification techniques have failed to materialize.
In the early 1970's, as large scale integrated circuit (LSI) technology took form in connection with metal oxide semiconductor (MOS) devices, a bucket brigade device (BBD) and a CCD were soon available as charge transfer devices (CTDs). From that time on, continued research in the field of solid state image sensors has remained active.
Generally, the structure of a CCD is simple. A plurality of MOS diodes are formed in uniform arrangement along the surface of a semiconductor substrate. When an inverting voltage is applied to a MOS diode, two states are obtained. A non-equilibrium state enlarges the deep depletion region beneath the surface of the semiconductor substrate. An equilibrium state is also obtained at which time minority carriers accumulate. When these two states are assigned digital logic levels of "0" and "1," respectively, a device having operating properties is realized. Hence, when a number of minority carriers are sequentially transferred from the non-equilibrium state to the equilibrium state, the result is a potential analog signal effect. Consequently, the above described two states make possible wide application of solid state image sensor type technologies.
In a solid state image sensor, the operations of photoelectrically converting, accumulating, scanning, and reading-out of such electric charges is realized on a single chip. Among the different solid state image sensors, the CCD type finds wide utility because it exhibits good electrical and structural characteristics.
The CCD type solid state image sensor has a photo sensing portion which includes either a PN junction photodiode or a MOS capacitor. The image sensor also has both a transfer portion, which includes a CCD shift register, and an output circuit portion.
When light is input to the photo sensing portion, photo energy is converted into an electrical charge to be accumulated and then sent to the transfer portion during a field shift. In turn, charges are accumulated in the corresponding transfer portion. When transfer pulses are sequentially applied to transfer gate electrodes, the charges are sequentially transferred to regions below adjacent electrodes. A sequential charge transfer is a function of the depth of depletion layers beneath the surface of the semiconductor substrate. In response to a series of transfer pulse voltages, signals introduced as charges at transfer portion regions are shifted to regions below adjacent electrodes until finally transferred to the output circuit portion.
As described above, the structure of a CCD having a transfer portion is very simple. However, because information is represented by a quantity of electric charges transferred within the body of the semiconductor substrate, completeness and accuracy of charge transfer becomes an important factor.
Transfer efficiency, defined as the ratio between an initial charge and a transferred charge, is an important parameter for determining a charge transfer characteristic of a particular CCD. A buried channel CCD (BCCD), in which a channel is formed in the bulk semiconductor just beneath the semiconductor surface, has been used to improve a CCD's transfer efficiency since first introduced (see, H. W. Kent in Bell, Syst. Tech. J., 52, 1009, 1973). However, because a long minority carrier travel time across the transfer portion degrades electric field intensity between adjacent electrodes, a different CCD electrode structure is necessary capable of reducing minority carrier travel time.
Experimental results on the influence of gate electrode length on charge transfer efficiency is discussed in an article by John Y. Chen and C. R. Viswanathan, "Barrier lowering in short-channel CCD's, " IEEE Trans. Electron Device, ED-29, 1588, 1982. Such overlap-gate CCD structures have become common. An overlap-gate CCD structure reduces the electrode length and yields high density of integration. The manufacturing method of a conventional overlap-gate CCD is illustrated in prior art FIGS. 1 through 4.
First, as shown in FIG. 1, oxidation film 12 and silicon nitride film 13 are sequentially laminated on a semiconductor substrate 11 to provide a dielectric layer of a transfer gate electrode. In turn, after a polycrystal silicon layer is formed thereon, conventional photolithography and etching processes are used to form first transfer gate electrodes 14.
Subsequently, as shown in FIG. 2, when the remaining polysilicon layer constituting first transfer gate electrodes 14 is thermally oxidated, insulation oxidation film 15 is formed to a constant thickness over the surface and along the side walls of first transfer gate electrodes 14. At this time, formation of insulation oxidation film 15 results in a characteristic oxidation film growth speed difference between silicon nitride film 13 and the remaining polysilicon layer constituting the first transfer gate electrodes 14.
The thermal oxidation method is certainly a desired insulation oxidation film formation method. However, it has a drawback in that this method yields a structurally weak portion (portion 1A of FIG. 2) that provides an insufficient insulation characteristic.
As shown in FIG. 3, after a second polysilicon layer is formed over the overall surface of an upper portion of the substrate, a polysilicon layer having a wing-shaped pattern results. Using a conventional photolithography and etching process, portions of the second polycrystal silicon layer are formed to overlap adjacent first transfer gate electrodes 14, thus forming second transfer gate electrodes 16.
In FIG. 4, a partial cross-sectional view of enlarged portion 1A, described above as a structurally weak portion in FIG. 2, is shown in closer detail. The conventional overlap-gate structure of FIGS. 1 to 4 is simple to manufacture and results in a highly integrated gate electrode structure having short electrode lengths. However, such a conventional CCD contains the following drawbacks.
First, when insulation oxidation film 15 is formed using a thermal oxidation process, the growth speed of the oxidation film 15 is materially reduced as a result of inherent material property characteristics of silicon nitride film 13. Consequently, edge portion 1A of each first transfer gate electrode 14 disposed adjacent to silicon nitride film 13 is too structurally weak to protect against direct leakage currents generated by, for example, a pinhole. This is because insulation oxidation film 15, between first and second transfer gate electrodes 14 and 16, is too thin.
Secondly, when the first polycrystal silicon layer is processed by a photolithography and etching process to form first transfer gate electrodes 14, portions of silicon nitride film 13 along lower portions of second transfer gate electrode 16, become over-etched. The result is a thickness difference along the lateral surface width of silicon nitride film 13 which is made particularly thin along these over-etched portions.
In turn, a difference in dielectric capacitance exits due to the difference in thickness between first and second transfer gate electrodes 14 and 16 with semiconductor substrate 11. This difference in dielectric capacitance scatters linearity due to an asymmetry of electric charge transfer below respective gate electrodes as well as changes a potential well structure below respective gate electrodes. As a result, device characteristics such as, for example, CCD transfer efficiency is degraded.
Thirdly, the surface of silicon nitride film 13 that is exposed between first transfer gate electrodes 14 is damaged and polluted during a dry etching process (performed when first transfer gate electrodes 14 are formed), as well as during a subsequent thermal oxidation process. As a result, the dielectric characteristics of second transfer gate electrodes 16 are significantly degraded.